IBIS Macromodel Task Group Meeting date: 28 Feb 2011 Members (asterisk for those attending): Agilent: * Fangyi Rao Radek Biernacki Altera: * David Banas Ansys: Samuel Mertens Dan Dvorscak * Curtis Clark Arrow Electronics: Ian Dodd Cadence Design Systems: Terry Jernberg * Ambrish Varma * Feras Al-Hawari Celsionix: Kellee Crisafulli Cisco Systems: Ashwin Vasudevan Syed Huq Ericsson: Anders Ekholm IBM: Greg Edlund Intel: Michael Mirmak LSI Logic: Wenyi Jin Maxim Integrated Products: * Mahbubul Bari Mentor Graphics: * John Angulo Zhen Mu * Arpad Muranyi Vladimir Dmitriev-Zdorov Micron Technology: Randy Wolff NetLogic Microsystems: Ryan Couts Nokia-Siemens Networks: * Eckhard Lenski QLogic Corp. * James Zhou Sigrity: Brad Brim Kumar Keshavan Ken Willis SiSoft: * Walter Katz Todd Westerhoff Doug Burns * Mike LaBonte Snowbush IP: Marcus Van Ierssel ST Micro: Syed Sadeghi Teraspeed Consulting Group: Scott McMorrow * Bob Ross TI: Casey Morrison Alfred Chong Vitesse Semiconductor: Eric Sweetman Xilinx: Mustansir Fanaswalla The meeting was lead by Arpad Muranyi ------------------------------------------------------------------------ Opens: - Mike: Unable to attend next -------------------------- Call for patent disclosure: - None ------------- Review of ARs: - Arpad revise BIRDs 117 and 118 - In progress ------------- New Discussion: New BIRD draft on nameing rules: - Walter: This was to see if it important enough to go into 5.1 - It might be deferred Analog BIRD 144.2: - Arpad: I don't see a way to use [External Model] with Touchstone inside - Feras: We can work on this for next week - Arpad: One question is about s-params that have more ports than a model can use - Feras: Boundary conditions for those nodes were defined in a previous revision - Boundary conditions for connected nodes are not done - Fangyi: In SPICE unused nodes are considered a broken circuit Analog BIRD 145.1: - Walter showed an ASCII circuit diagram from BIRD 145.1 - Walter: How do I know whether to apply [Pullup Reference] from ideal source or Vcc3? - Is Vcc3 receiving power for the buffer? - Feras: If there is a port mapping it is externally supplied - If not add ideal V sources - Walter: What if my termination is a resistor between Vcc3 and pad? - Maybe that is what Vcc3 is intended for - Feras: We can assume the model developer took care of everything - Arpad: We need to define whether the voltage is to be supplied - Bob: The voltage should always be supplied at Vcc3 - Arpad: How do we know when to supply sources and wehn not to at the buffers? - Bob: A regular model provides it's own power - A SPICE model needs outside power - Feras: vcc will supply power to vcca2 - Walter: It is a black box, we don't know that - Arpad: If the external circuit has no Vcc port there will be no power - Then [External Circuit] can't be used for ODT - Walter: A better way would be to add a B element to IBIS-ISS and use BIRD 116 - Feras: We should not have to wrap legacy IBIS I/Os - Arpad: A single IBIS-ISS would be needed - Walter: I am proposing [External Model] with IBIS-ISS - Arpad: You can't have extra nodes there for elaborate ODT circuits - Example 2 can't have ODT because there is no power/ground - IBIS-ISS could have an ideal source - Bob: The voltages are already defined in IBIS - The model would be useless for SSO if ideal supplies are used - There is a question about whether this overrides [Pin Mapping] - Walter: We need a clear rule about where to supply [Pullup Reference] - Arpad: In legacy IBIS how do we know if a [Model] needs power? - Bob: The HSPICE B element has an option - Arpad: With [Pin Mapping] we have an indication where buffer power is supplied - Feras: For SSN we use [Pin Mapping] - Otherwise we use ideal power - Walter: If I don't have a power distribution circuit I supply it automatically - IBIS doesn't support that - Arpad: We might have the same question about how to power models with legacy IBIS - Ambrish: vcc supplies power to vcca1 - Arpad: There is no way to know that - The rule should be that the [External Circuit] always powers the buffers - Feras: We give two ways to do it, one for SSN and one for other simulations - Walter: It still is not clear - Arpad: The tool never has to power the model - Walter: Then it can't be used for ODT - Arpad: It can use the same supplies for ODT - Walter: Not if the [External Circuit] is used just for ODT, no package - James: How do we so ODT today? - Feras: Sometimes with [Model Selector] - Arpad: It can be built into I-V curves - [External Circuit] allows for more complex circuits with frequency dependency - James: There should be a rule that the [External Circuit] has to receive power - Walter: And all nodes have to be hooked up - Arpad: Does the user have to connect pin 18 to power on a schematic? - Feras: Some pin mapping has to indicate that power is needed - The netlister will detect that pin 18 is connected to a power net - Mike: You said your tool does that only for SSO simulations - James: IBIS 5.0 says the user can define any number of ports on a circuit - Arpad: We need to add a rule that power is always supplied by the tool - Bob: Tools already have controls to decide where power comes from - Here we don't know if the external circuit provides model power - James: We should supply pin power whenever [External Circuit] is used Walter: I will miss the next two meetings Meeting ended. ------------- Next meeting: 06 Mar 2011 12:00pm PT Next agenda: 1) Task list item discussions ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives